Keeping pace with the development of semiconductor, efforts to integrate more elements onto one semiconductor chip in high degree has been actively progressing. Particularly, in DPAM (Dynamic Random Access Memory) cell, various Cell structures have been proposed to minimize the size of a element.
For high integration, it is preferable that a memory cell is composed of one transistor and one capacitor in a view to minimize the occupied area on a chip. In a memory cell composed of one transistor and one capacitor as mentioned before, a signal charge is stored in a storage node of a capacitor, which is connected to a transistor (switching transistor). Consequently, if the size of a memory cell is decreased for high integration of semiconductor memory, because the size of the capacitor has to be decreased accordingly, the number of charges which can be stored in a storage node have to also decrease.
Therefore, in order to transmit a desired signal without any malfunction, the capacitor storage node of a memory cell has to have a surface area greater than a certain predetermined value to secure a capacitor capacity required for the transmission of a signal.
Thus, a capacitor storage node has to have relatively large area within the limited area of a semiconductor substrate to decrease the size of a memory cell.
Of the various memory cell construction proposed to increase the surface area of a capacitor storage node, a stack capacitor is a capacitor structure having the advantages of being favorable for high integration while being influenced by soft error little.
Further a memory cell having stacked capacitor also has the advantages of being suitable for mass production with a relatively simple process.
Finned capacitor published in "IDEM pp. 592-295, 1988" by Ema et al., one of the stacked capacitor to increase the capacity, is to be explained hereinafter, referring to FIGS. 1(a) to 1(g).
First, as shown in FIG. 1(a), after forming a memory cell transistor composed of gate pole 1 and source and drain 2 on a semiconductor substrate 100, deposit a nitride film 3 above the memory cell transistor as shown in FIG. 1(b), then form a first oxide film 4, a first poly silicon layer 5, a second oxide film 6 successively thereon as shown in FIG. 1(c), and etch the second oxide film 6, the first poly silicon layer 5, and the first oxide film 4 selectively thereafter to form a contact hole as shown in FIG. 1(c).
Next, as shown in FIG. 1(d), after deposition of a second poly silicon layer on all over the surface of above resultant, carry out a selective etching of the second poly silicon layer 7, the second oxide film 6, and the first poly silicon layer 5, to form a finned capacitor storage node as shown in FIG. 1(e).
Next, as shown in FIG. 1(f), after removing the second oxide film and the first oxide film with a wet etching, form a capacitor dielectric film 8 on all over the capacitor storage node having been formed in above process as shown in FIG. 1(g), then form a capacitor plate pole 9 on all over the capacitor dielectric film 8 completing a capacitor of a semiconductor memory.
In a capacitor having a finned storage node described above, the more the number of stacked fins increase, the greater the possibility of defect development, due to weakening of the mechanical strength of the poly silicon layer in the center part connected with each stacked layer and serving to support the stacked layers.
And, because the more the number of stacked fins increase, the greater the aspect ratio of a contact hole which is provided to connect a memory cell transistor with a capacitor become, the coating property of the poly silicon supporting film which is the uppermost conduction layer forming stacked capacitor storage node is impaired.
To solve these problems, H. Gotou et al. invented a technology in which stacked films are provided to be able to be supported by a conductive side wall connecting fin shape stacked films in one corner of a conductive base layer connected to a source and drain of a memory cell transistor (U.S. Pat. No. 5,126,810).
Forgoing technology is to be explained hereinafter, referring to FIGS. 2(a) to 2(f).
First, as shown in FIG. 2(a), after forming a memory cell transistor composed of gate pole 11 and source and drain area 12 on a semiconductor substrate 100 by a general MOS transistor production process, form inter-layer insulation film 13, etch preventing film 14 and buffer layer 15 successively with CVD (Chemical Vapor Deposition) method on all over the substrate on which the memory cell transistor has been formed.
Then, etch the buffer layer 15, etch preventing film 14 and the inter-layer insulation film 13 selectively to form a contact hole exposing source(or drain) area 12 of the transistor, and carry out stacking of multi-layer poly silicon layers 16, 18 and 20 and multi-layer oxide films 17, 19 and 21 alternatively thereafter.
Next, as shown in FIG. 2(b), form a desired pattern by selective etching of the alternatively stacked multi-layer poly silicon layers 16, 18 and 20 and the multi-layer oxide films 17, 19 and 21.
Next, as shown in FIG. 2(c), after deposition of poly silicon on all over the surface of above resultant, form a poly silicon side wall 22 with anisotropic etching. The poly silicon side wall 22 formed as above supports the multi-layer poly silicon layers 16, 18 and 20 stacked between the multi-layer oxide films 17, 19 and 21 as well as acts as a electric communication passage.
Next, as shown in FIG. 2(d), after deposition of photo resist 23 on all over the surface of above resultant, carry out patterning with a photo etching process to expose one side of the formed poly silicon side wall 22, and carry out etching of the exposed one side poly silicon side wall 22 thereafter.
Next, as shown in FIG. 2(e), after removing the photo resist pattern and the buffer layer, the multi-layer oxide films 17, 19 and 21 are removed so as to complete a capacitor storage node composed of multi-layer poly silicon layers 16, 18 and 20 and poly silicon side wall 22 supporting the multi-layer poly silicon layers 16, 18 and 20.
Next, as shown in FIG. 2(f), after forming capacitor dielectric film 24 on all over the capacitor storage node, carry out deposition and patterning of a conductive material on all over the surface of the dielectric film 24 to form a capacitor plate pole 26 completing a capacitor.
The prior art described above has, because load is concentrated on the side wall of the conductive base layer(poly silicon layer 16) above the contact hole provided for connecting the transistor and the capacitor, a tendency that mechanical strength of the stacked storage node become weak, and difficulties in the processes that the degree of etching in the anisotropic etching for forming the poly silicon side wall has to be controlled precisely to prevent the stacked film above from being etched.